PhD researcherPanagiotis.Theocharis [AT] elis.UGent.be
System Software Lab
Computing Systems Lab (CSL)
Electronics and Information Systems (ELIS) department
Sint Pietersnieuwstraat 41
Split Compilation for Accelerator-based Multicores
Future embedded devices are foreseen to consist of multicore and manycore processors of which a number of cores will be programmable accelerators that offer many different instruction sets. Writing code for specific accelerator instruction sets is unproductive, however. Therefore we propose to virtualize the ISA of such accelerators to a bytecode.
To enable the flexible deployment of “bytecoded” applications, the bytecode should be architecture-independent or neutral, and a retargetable deployment-time compiler should be able to map that neutral bytecode onto the different accelerators effectively and efficiently, i.e., it should do a good compiler job fast.
Today, however, no compiler tool chains with deployment-time code generation exist that provide portable performance for a range of accelerators that is wide enough to support accelerating a large range of application kernels. As a result, a fundamental problem for the transition to accelerator-based manycore designs is the development cost and inflexibility of software with the current state of the art in compiler techniques.
The strategic goal of my research project is to design and develop a compiler tool flow that:
- supports accelerator-based manycore processor
- enables the integration and reuse of independently developed software components
- supports the flexible management of accelerator resources
The long term goal is to create larger, economically viable markets for accelerator designs, and to increase the productivity of software developers and the flexibility of the applications.
My research focuses on the development of the necessary compiler technology to reach these goals. The proposed technology builds on the concept of split compilation, where a static, design-time compiler can spend a long time analysing a program to extract all useful knowledge from it, and to annotate the neutral bytecode it generates with that knowledge. A deployment-time compiler will then use the annotations to produce binary code for specific architectures efficiently and effectively. Furthermore, a design-time tool will generate compiler strategies tuned for specific architectures.
In short, the deployment-time, retargetable compiler will be fed with compiler strategies already tuned in advance for the underlying hardware and with compiler strategies derived from the source code. Using these strategies, I hope to demonstrate that the deployment-time compiler can retarget itself to different architectures without needing to explore a large compiler optimization space that is currently explored in long running, static retargetable compilers.
For more information, click on the link below:
Contact person for Projects:
|Machinaal exploreren van state-of-the-art processorontwerpsruimten||Master thesis||2013|
|Smart-camera toepassingen op state-of-the-art CGRA processors||Master thesis||2013|
|Een LLVM compiler voor state-of-the-art CGRA processors||Master thesis||2013|
|Machinaal lerende compilers voor CGRA architecturen||Master thesis||2013|
Publications to Appear
- Panagiotis Theocharis and Bjorn De Sutter A bimodal scheduler for coarse-grained reconfigurable arrays ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, Vol. 13(2), pp. 26 (2016)